Computer systems typically employ one or more interconnects to facilitate communication between system components, such as between processors and memory. Interconnects and/or expansion interfaces may also be used to support built-in and add on devices, such as IO (input/output) devices and expansion cards and the like. For many years after the personal computer was introduced, the primary form of interconnect was a parallel bus. Parallel bus structures were used for both internal data transfers and expansion buses, such as ISA (Industry Standard Architecture), MCA (Micro Channel Architecture), EISA (Extended Industry Standard Architecture) and VESA Local Bus. In the early 1990's Intel® Corporation introduced the PCI (Peripheral Component Interconnect) computer bus. PCI improved on earlier bus technologies by not only increasing the bus speed, but also introducing automatic configuration and transaction-based data transfers using shared address and data lines.
As time progressed, computer processor clock rates where increasing at a faster pace than parallel bus clock rates. As a result, computer workloads were often limited by interconnect bottlenecks rather than processor speed. Although parallel buses support the transfer of a large amount of data (e.g., 32 or even 64 bits under PCI-X) with each cycle, their clock rates are limited by timing skew considerations, leading to a practical limit to maximum bus speed. To overcome this problem, high-speed serial interconnects were developed. Examples of early serial interconnects include Serial ATA, USB (Universal Serial Bus), FireWire, and RapidIO.
Another standard serial interconnect that is widely used is PCI Express, also called PCIe, which was introduced in 2004 under the PCIe 1.0 standard. PCIe was designed to replace older PCI and PCI-X standards, while providing legacy support. PCIe employs point-to-point serial links rather than a shared parallel bus architecture. Each link supports a point-to-point communication channel between two PCIe ports using one or more lanes, with each lane comprising a bi-directional serial link. The lanes are physically routed using a crossbar switch architecture, which supports communication between multiple devices at the same time. As a result of its inherent advantages, PCIe has replaced PCI as the most prevalent interconnect in today's personal computers. PCIe is an industry standard managed by the PCI-SIG (Special Interest Group). As such, PCIe pads are available from many ASIC and silicon vendors.
The PCI specification introduced the concept of a posted transaction to improve performance. However, this also resulted in a set of transaction ordering rules to ensure data coherency and prevent deadlocks. Data coherency is required for correct operation of Producer-Consumer model. The transaction ordering rules also exist PCI-Express interconnects. The transaction ordering rules are also embedded in on-die interconnects to connect various PCI/PCIe devices. One of the characteristics of PCI based interconnects is write data and read return data share the same data path in each direction.
While Intel®-based architectures (e.g., IA-32) have dominated the desktop, server, laptop, and notebook markets, the most common architectures employed by devices in the mobile space (e.g., mobile phones and tablets) are ARM-based architectures. Platforms based on ARM-based architectures typically employ one or more of Advanced Microcontroller Bus Architecture (AMBA) (e.g., Advanced High-performance Bus (AHB)), Open Core Protocol (OCP), and Basic Virtual Component Interface (BVCI) interconnects. These interconnects have a completely different set of transaction ordering rules (as compared with PCI/PCIe), and typically employ separate write and read return data buses. As a result, when a PCI-based on-die interconnect is used to attach a device employing one of these ARM-based interconnects or vice-versa, several problems related to data coherency arise due to differences in transaction ordering rules and interconnect topologies. Accordingly, this makes it difficult to mix PCI/PCIe and ARM-based interconnects and devices.